Updated Program July, 13

 01/09 - 30/09/2020

Plenary talks:

Horizontal, stacked or vertical silicon nanowires: does it matter from a low-frequency noise perspective? - Eddy Simoen (IMEC, Leuven, Belgium)

Reflections on the Past, Present, and Future of Device Research - Mark Lundstrom (Purdue University, Indiana, USA)

Novel Electron Devices for the Quantum Era - Cezar Zota (IBM Zurich, Switzerland)

Fabrication and characterization of GaN-based nanostructure field-effect transistors (FETs) - Jung-Hee Lee (Kyungpook National University, South Korea)

Characterization of nanometer scale devices (I)

Temperature influence on analog figures-of-merit of nanosheet nMOSFET devices for sub-7nm technology node - Vanessa Cristina Pereira da Silva, University of São Paulo

 Electrostatics and channel coupling on 28 nm FD-SOI for cryogenic applications - Bruna Cardoso Paz, Laboratoire d'électronique et de technologie de l'information

Influence of Fin Width Variation on the Electrical Characteristics of n-Type Junctionless Nanowire Transistors at High Temperatures - Thales Augusto Ribeiro, Centro Universitário FEI

Characterization of nanometer scale devices (II)

 From 1.8V to 0.19V voltage bias on analog spiking neuron in 28nm UTBB FD-SOI technology - Valérian Cinçon, Stmicroelectronics

Correlation between the NBTI Effect and the Interface Traps Density in Junctionless Nanowire Transistors - Nilton Graziano Junior, University Center FEI, Department of Electrical Engineering– São Bernardo do Campo, - Rodrigo Trevisoli, University Center FEI, Department of Electrical Engineering– São Bernardo do Campo,

Impact of Channel Implant Variation on RTN and Flicker Noise - Yannick Raffel, Fraunhofer-Institut für Photonische Mikrosysteme

Characterization of nanometer scale devices (III)

Y-Function Based Methodology for Accurate Statistical Extraction of HEMT Devices Parameters for GaN Technology - Roméo KOM KAMMEUGNE, Univ. Grenoble Alpes, F-38000, France, CEA, LETI, MINATEC Campus, F-38054 Grenoble, France

Evaluation of Analog Characteristics of n-Type Vertically Stacked Nanowires - Genaro Mariniello, Centro Universitário FEI - Marcelo Antonio Pavanello, Centro Universitário FEI

Advanced and Innovative SOI Architectures (I)

New embedded resistance/ gated diode on thin film silicon BIMOS device for advanced ESD protection in FD-SOI technology - Philippe Galy, Stmicroelectronics - geoffrey Delahaye, STMicroelectronics

SPAD FDSOI cell optimization for lower dark count rate achievement - Dylan Issartel, INL - Institut des Nanotechnologies de Lyon

 Effect of Heat Sink in Back-End of Line on Self-Heating in 22nm FDSOI MOSFETs - Arka Halder, Université Catholique de Louvain

Advanced and Innovative SOI Architectures (II)

Logic Elements and Crossbar Architecture Based on SOI Two-Gate Ferroelectric Transistors - Mikhail Tarkov, Rzhanov Institute of Semiconductor Physics SB RAS - Vladimir Popov, Rzhanov Institute of Semiconductor Physics SB RAS

Nanoribbon charge-based biosensor using gateless UTBB BESOI pMOSFET - Leonardo Shimizu Yojo, University of São Paulo

Threshold voltage modulation of AlGaN/GaN MIS-FinFETs with sub-60 mV/decade subthreshold swing - QUAN DAI, Kyungpook National University [Daegu]

Revisited parasitic bipolar effect in FDSOI MOSFETs: mechanism, gain extraction and circuit applications - guoqing wang, College of Big Data and Information Engineering, Guizhou University, Key Laboratory of Silicon Device and Technology, Chinese Academy of Sciences, Institute of Microelectronics, Chinese Academy of Sciences - Fanyu Liu, Key Laboratory of Silicon Device and Technology, Chinese Academy of Sciences, Institute of Microelectronics, Chinese Academy of Sciences - Bo Li, Key Laboratory of Silicon Device and Technology, Chinese Academy of Sciences, Institute of Microelectronics, Chinese Academy of Sciences

 Pseudo-MOSFET transient behavior: experiments, model and substrate effect - xu zhang, Institute of Microelectronics, Chinese Academy of Sciences, Key Laboratory of Silicon Device and Technology, Chinese Academy of Sciences, University of Chinese Academy of Sciences - Fanyu Liu, Institute of Microelectronics, Chinese Academy of Sciences, Key Laboratory of Silicon Device and Technology, Chinese Academy of Sciences - Bo Li, Institute of Microelectronics, Chinese Academy of Sciences, Key Laboratory of Silicon Device and Technology, Chinese Academy of Sciences - Jing Wan, State key lab of ASIC and System, Fudan University

Beyond and More than Moore devices and applications

CVD-grown back-gated MoS2 transistors - Carlos Marquez, Nanoelectronics Research Group (CITIC-UGR), Department of Electronics, University of Granada, 18071, Granada, Spain, Tyndall National Institute [Cork] - Norberto Salazar, Nanoelectronics Research Group (CITIC-UGR), Department of Electronics, University of Granada, 18071, Granada, Spain - Francisco Gamiz, Nanoelectronics Research Group (CITIC-UGR), Department of Electronics, University of Granada, 18071, Granada, Spain

Modeling Selectivity and Cross-sensitivity in membrane-based potentiometric sensors - Leandro Julian Mele, DPIA University of Udine

Single and Triple Insulator Tunnel Rectifiers for Infrared Energy Harvesting - Serdar Tekin, Department of Electrical Engineering and Electronics, University of Liverpool

Large-Scale CMOS Compatible Process for Silicon Nanowires Growth in the Si-BC8 Phase - Ivan Mazzetta, Dipartimento di Ingegneria dellÍnformazione, Elettronica e Telecomunicazioni [Roma]

Contact between CMOS circuits and cell membrane by silicon nanowires - Fabrizio Palma, Rome University La Sapienza

Suppressing crosstalk in the photoelectron in-situ sensing device (PISD) by double SOI - Muhammad Arsalan, Fudan university

III-V semiconductor and memories oriented applications (I)

AlGaN/GaN MISHEMT analysis from an analog point of view up to 150 C - Paula Agopian, São Paulo State University

Ultra-Low Power Scaled III-V-on-Si 1T-DRAMs With Quantum Well Heterostructures - Clarissa Convertino, IBM Zurich Research Laboratory

III-V semiconductor and memories oriented applications (II)

MIS structures with interfacial graphene for ReRAM applications: a nanoscale and device level characterization - Sergi Claramunt, Electronic Engineering Department, Universitat Autònoma de Barcelona

 Resistive Switching Performance of Bilayer RRAM Device with Solution-based Dielectric - Zongjie Shen, University of Liverpool, Xián Jiaotong-Liverpool University [Suzhou]

Reduced Current Spin-Orbit Torque Switching of a Perpendicularly Magnetized Free Layer - Viktor Sverdlov, Christian Doppler Laboratory for Nonvolatile Magnetoresistive Memory and Logic at the Institute for Microelectronics

Simulations and Modelling (I)

Vmin Prediction for Negative Capacitance MOSFET based SRAM - Tapas Dutta, University of Glasgow

Thermal broadening of the electron mobility distribution in FD-SOI MOSFETs - Gilberto Umana-Membreno, Dept of Electrical, Electronic and Computer Engineering, The University of Western Australia [Crawley WA]

Poisson-Schrodinger simulation of inversion charge in FDSOI MOSFET down to 0K – Towards compact modeling for cryo CMOS application - Mohamed Aouad, CEA-LETI

Compact Modeling of 3D Vertical Junctionless Gate-all-around Silicon Nanowire Transistors - Chhandak Mukherjee, Laboratoire de líntégration, du matériau au système

Simulations and Modelling (II)

 Comprehensive Modeling of Coupled Spin and Charge Transport through Magnetic Tunnel Junctions - Viktor Sverdlov, Christian Doppler Laboratory for Nonvolatile Magnetoresistive Memory and Logic at the Institute for Microelectronics, TU Wien

Efficient Implementation of S/D tunneling in 2D MS-EMC of Nanoelectronic Devices Including the Thickness Dependent Effective Mass - Cristina Medina-Bailon, University of Glasgow - Carlos Sampedro, University of Granada

Schottky-Barrier FET Ultra-Low-Power Diode - Mike Schwarz, NanoP, THM University of Applied Sciences - Alexander Kloes, NanoP, THM University of Applied Sciences - Denis FLANDRE, Université Catholique de Louvain

High Dielectric Constant Sub – Nanometric Laminates of Binary Oxides for the Application in High-Density Capacitances - Mudit Upadhyay, CRISMAT

Poster Session

Annealing effects on the structure of Germanium Antimony Tellurium - HATUN CINKAYA YILMAZ, TUBITAK- BILGEM, 41470, Gebze / Kocaeli, Turkey

Characteristic C-V profile as a signature for electrostatic doping in FD-SOI - Gaurav Gupta, University of Twente

Current hysteresis in SOS Heterostructures with Interlayer Silicon Oxide - Valentin Antonov, A.V. Rzhanov Institute of Semiconductor Physics

Frequency Modulated C-V Characteristics Shift in Double-layer High-k Gate Stack MIS Devices - Andrzej Mazurak, Warsaw University of Technology

Incorporation of silicon-carbide (SiC) nanocrystals in the MIM structures based on pulsed-DC reactively sputtered HfOx layers - Robert Mroczyński, Warsaw University of Technology [Warsaw]

 Modeling the Conduction Characteristics of Single Crystalline ZnO Nanowires Using Back-to-Back Schottky Barriers with Series Resistance - Enrique Miranda, Universitat Autònoma de Barcelona [Barcelona]

Modifying SOI properties by CO+ molecular ion implantation - Vladimir Popov, A.V. Rzhanov Institute of Semiconductor Physics

Operational Transconductance Amplifier Designed with SiGe-source Nanowire Tunnel-FET using Experimental Lookup Table Model - Alexandro de Moraes Nogueira, University of São Paulo

Optimization of the Dual-Technology Back-Enhanced Field Effect Transistor - Carlos Augusto Bergfeld Mori, University of Sao Paulo

Phase transformation in ALD hafnia based layers for silicon-on-ferroelectric devices - Andrey Miakonkikh, Valiev Institute of Physics and Technology RAS, Moscow

Resistive switching performance of solution-processed RRAM under different precursor concentrations

Revisiting an influence of island edge on electrical characteristic of pseudo-MOSFET method - Shingo Sato, Kansai University

Simulation of gated GaAs-AlGaAs resonant tunneling diodes for tunable terahertz communication applications - Vihar Georgiev, University of Glasgow

Study of the manufacture uncertainty impact of the hybrid SET-FET circuit - Esteve Amat, Institute of Microelectronics of Barcelona (IMB-CNM, CSIC)

TCAD comparison of planar and recessed gate reconfigurable FETs - Sehyun Kwon, Hanyang University

The Current Model for FOI FinFETs with Back- Gate Bias - Fengyuan Zhang, Institute of Microelectronics, Chinese Academy of Sciences, University of Chinese Academy of Sciences [Beijing], Key Laboratory of Silicon Device and Technology, Chinese Academy of Sciences

Thermal Cross-Coupling Effects Analysis in UTBB Transistors - Fernando José Costa, Centro Universitário FEI - Rodrigo Trevisoli Doria, Centro Universitário FEI - Renan Trevisoli Doria, Universidade Federal Do ABC

Topologically Protected and Conventional Subbands in a 1T'-MoS2 Nanoribbon Channel - Viktor Sverdlov, Institute for Microelectronics, TU Wien

Trap identification on n-channel GAA NW FETs - Bogdan Cretu, Groupe de Recherche en Informatique, Image, Automatique et Instrumentation de Caen

Tunneling and Resonant Tunneling Effects in the Metal-Ultrathin Oxide-(n+)Silicon Structures - Wiśniewski Piotr, Center for Terahertz Research and Applications (CENTERA), Institute of High-Pressure Physics, Polish Academy of Sciences, Institute of Microelectronics and Optoelectronics, Warsaw University of Technology, Centre for Advanced Materials and Technologies CEZAMAT, Warsaw University of Technology

Ultrafast Carrier Dynamics in Black Silicon Quantum Pillars - SEREF KALEM, Bahcesehir University

Use of CMOS Image Sensor for early detection of ischemic and hemorrhagic stroke - Fabrizio Palma, Rome University La Sapienza

On-the-fly' measurements of CMOS inverters performance degradation under pulsed stress - Albert Crespo-Yepes, Universitat Autònoma de Barcelona [Barcelona]

3D Simulation Flow for a Snubber Device - Aubry Yves, Murata-Caen